1. Field of the Invention
The present invention relates to methods for erasing/programming a non-volatile electrically erasable memory, and more particularly to methods for opening the programming window of a non-volatile electrically erasable memory, such as an EEPROM or Flash memory.
2. Description of Related Art
EEPROM and Flash memories use floating gate transistors. A memory cell in a conventional EEPROM memory thus comprises a floating gate transistor (FIG. 1a) that includes a control gate 101, a floating gate 102, a source region 103, a drain region 104, an oxide layer 105 and a substrate region 106. The gate is said to be “floating” since it does not have any contact with the exterior that imposes a potential on it. The thickness of the oxide 105 between the floating gate 102 and the substrate region 106 is typically on the order of a few nanometers. This reduced thickness enables the passage of electrons by the tunnel effect.
In order to erase the cell, a high voltage is typically applied on the control gate 101 and a zero voltage is applied on the drain 104. The electrical field created causes electrons to migrate to the floating gate 102 by the tunnel effect. Electrons are then trapped on the floating gate. The cell is programmed by applying a high voltage to the drain 104 and a zero voltage to the control gate 101. The floating gate thus discharges.
Conventionally, the cells of an EEPROM memory are tested at the end of the manufacturing process, particularly by carrying out endurance tests. To enable these tests, a step is carried out to open the memory cell programming window. At the end of the manufacturing process, cells are in a blank state with charges included in the oxide of the floating gate transistor of the cell, which reduces the efficiency at which cells in service can be programmed or erased. Opening the memory cell programming window involves carrying out a sequence of memory cell erase/programming cycles in order to eliminate all charges from the oxide.
An EEPROM memory is provided with internal circuits that fix the programming or erasing time and voltage of the cells in a pre-defined manner. Conventionally, these circuits are activated to perform a series of erase/programming cycles for a predetermined total time. Thus, assuming that the cell programming time is 10 milliseconds, about a hundred cycles are carried out to obtain an exemplary window opening time of 1 second.
Voltages applied to the drain or to the control gate are generated by a state fixation voltage generator. FIG. 1b contains a timing diagram of the voltages generated by such a generator during an exemplary cell erase/programming cycle. A first erase pulse 110 comprises four phases:
1) a plateau 111 at a memory power supply voltage Vcc;
2) an increasing voltage ramp 112 between the voltage Vcc and a programming or erase voltage P, with a duration of 1 ms in this example, with the slope of the ramp being determined such that the electric field between the drain 104 and the floating gate 102 does not vary too quickly, so as not to deteriorate the cell;
3) a plateau 113 at the programming or erase voltage P, with a duration of 1 ms in this example; and
4) a falling front 114 during which the voltage P returns to the power supply value Vcc.
A consecutive programming step 210 comprises corresponding phases 211 to 214 that are identical to the phases in the erase step.
The generator pulses are applied selectively to the drain during programming, or to the gate of the floating gate transistor during erasing.
This type of EEPROM memory and window opening method have disadvantages. For example, for a given window opening time, the number of erase/write cycles to be made varies as a function of the cell programming time defined by the memory circuitry. For a given technology, different EEPROM memory series may have different programming times. Therefore the number of cycles in the method needs to be adapted to the programming time of each series, which makes this window opening step painstaking. The window opening step is done on several memories in parallel (for example, 8, 16 or 32), so consequently cell programming times have to be tested to determine the number of erase/write cycles to be applied.
Other disadvantages also appear from the user's point of view. For example, the programming time for memories in a particular series is variable, since it depends on contingencies in the manufacturing method. Memories in a particular series may thus have a completely different behavior due to these different programming times.
Moreover, internal circuits fixing the cell programming time are fixed and define a programming time that guarantees that each cell can be correctly erased or programmed for a given number of cycles corresponding to its life. The user does not have any simple means for improving the life of the memories.